1. Field of the Invention
The present invention relates to active matrix substrates used in matrix type liquid crystal display devices, EL (electroluminescence) display devices, etc. More specifically, the present invention relates to an active matrix substrate which includes: a plurality of data signal lines and a plurality of scanning signal lines disposed in a grid pattern that provide intersections; and a matrix of pixel circuits each corresponding to one of the intersections and having a switching element provided by, e.g., a field-effect transistor such as a thin-film transistor, and a voltage holding capacitor; and relates also to a display device which includes the active matrix substrate.
2. Description of the Related Art
Active matrix substrates are utilized widely in active matrix type display devices such as liquid crystal display devices and EL display devices, as well as active matrix type sensors. In particular, liquid crystal display devices which include display pixels each having a switching element provided by a field-effect transistor such as a thin-film transistor (hereinafter abbreviated as “TFT”) gather special attention because of their ability to provide superb display image without crosstalk even if the number of display pixels is increased.
A matrix type liquid crystal display device such as the above includes, principally, a liquid crystal display panel and a drive circuit therefor. The liquid crystal display panel has a pair of electrode substrates sandwiching a liquid crystal layer, and each of the electrode substrates has its outer surface provided with a polarizer plate.
One of the electrode substrates is an active matrix substrate called a TFT substrate. The TFT substrate includes an insulating substrate provided by glass for example, on which a plurality of data signal lines and a plurality of scanning signal lines are formed to intersect with each other. Further, a plurality of auxiliary capacity lines are formed in parallel to the scanning signal lines. Also, a plurality of pixel circuits, each corresponding to one of the intersections made by the data signal lines and the scanning signal lines, are formed in a matrix pattern. Each of the pixel circuits includes: a pixel electrode which corresponds to a pixel as a constituent of an image to be displayed; a pixel capacity formed by the pixel electrode and an opposed electrode and other components to be described later; and a TFT serving as a switching element. The other of the electrode substrates is called an opposed substrate, and is provided by an insulating, transparent substrate such as glass, and its entire surface is provided with an opposed electrode and an alignment film formed in this sequence.
An active matrix type liquid crystal display device includes, as drive circuitry for the liquid crystal display panel of the above-described configuration, a scanning signal line drive circuit connected with the scanning signal lines, a data signal line drive circuit connected with the data signal lines, an auxiliary capacity line drive circuit connected with the auxiliary capacity lines, and an opposed electrode drive circuit connected with the opposed electrode.
The data signal line drive circuit generates, based on image signals received from an outside signal source for example, a plurality of data signals sequentially in the form of analog voltage which represent pixel values in each horizontal scanning line of the image to be displayed in the liquid crystal display panel, and applies these data signals respectively to the data signal lines in the liquid crystal display panel. The scanning signal line drive circuit sequentially selects the scanning signal lines in the liquid crystal display panel for each horizontal scanning period, and applies an active scanning signal (a voltage which turns ON the TFT in the pixel circuit) to the selected scanning signal line, in each frame period (each vertical scanning period) for displaying an image on the liquid crystal display panel. The auxiliary capacity line drive circuit and the opposed electrode drive circuit apply signals to the auxiliary capacity lines and the opposed electrode respectively, and these signals give electric potentials that serve as baseline voltages for the voltages to be applied to the liquid crystal layer of the liquid crystal display panel.
As described above, the data signal lines are supplied with respective data signals, and the scanning signal lines are supplied with respective scanning signals, whereby the pixel electrode in each pixel circuit of the liquid crystal display panel is supplied with a voltage representing the value of the pixel for the image to be displayed via the TFT, with the electric potential at the opposed electrode serving as the baseline voltage, and the supplied voltage is held at the pixel capacity in each pixel circuit. Thus, a voltage which is equal to the potential difference between the pixel electrode and the opposed electrode is applied to the liquid crystal layer. By controlling optical transmittance based on this applied voltage, the liquid crystal display panel displays an image represented by the image signals received from e.g. an outside signal source.
When manufacturing an active matrix substrate for use in such a liquid crystal display device as described above, the manufacturing process makes use of photolithography to form patterns of electrodes, wiring, insulation films, etc. for implementing the scanning signal lines, the data signal lines, the TFT, etc. on an insulating substrate made of glass for example. When manufacturing a large active matrix substrate for use in a liquid crystal display device which has a large display screen, the area of the insulating substrate on which the patterns are to be formed is divided into a plurality of regions, and an exposure step is performed separately, i.e. individually to each of the segmented regions. Generally, the exposure step, performed by using exposure equipment such as a stepper, involves various error factors in terms of stage positioning accuracy, focus level, etc., and these factors cause inconsistency in relative positions (positional relationships) between the patterns (layers). This means that the relative positional inconsistency between the patterns in different layers (hereinafter called “pattern misalignment”) differs in its extent and direction, among the segmented regions into which the entire screen region was divided for the purpose of separate exposure.
FIG. 22 shows a configuration of a pixel circuit in a TFT substrate serving as an active matrix substrate used in a liquid crystal display device as described above. Each pixel circuit P(i, j) corresponds to one of the intersections made by the data signal lines and the scanning signal lines, and includes: a TFT 16 which has a source electrode connected with a data signal line S(i) passing the corresponding intersection; a gate electrode which is connected with a scanning signal line G(j) passing the same intersection; and a pixel electrode 18 connected with a drain electrode of the TFT 16. The pixel electrode 18 and an opposed electrode Ec form a liquid crystal capacity Clc. The pixel electrode 18 and an auxiliary capacity line CS(j) provided along the scanning signal line G(j) form an auxiliary capacity Cs, and the pixel electrode 18 and the scanning signal line G(j) form a parasitic capacity Cgd.
The parasitic capacity Cgd is an electrostatic capacitance between the gate electrode and the drain electrode of the TFT 16a in each pixel circuit P(i, j) (hereinafter, this parasitic capacity Cgd may also be called “gate-drain capacity”), and its value depends on the area of overlap resulted from the lithographical patterning steps in the above-described manufacturing process, or more specifically, depends on the area of overlap (hereinafter, called “the area of overlapping”) made by the gate electrode (or gate wiring as the scanning signal lines) and the drain electrode (or the pixel electrode 18) via the insulation layer. As mentioned earlier, the extent and direction of pattern misalignment are different from one segmented region to another, depending on the region for which division was made for the separate exposure. In other words, the area of overlapping differs from one segmented region to another, and the value of parasitic capacity Cgd in the pixel circuits differs from one segmented region to another.
Also, since there is a parasitic capacity Cgd as described above between the scanning signal line G(j) and the pixel electrode 18 in each pixel circuit P(i, j) as shown in FIG. 22, the following phenomenon results. Specifically, if a data signal Vs(i) as shown in FIG. 23B is applied to the data signal line S(i), a fall of the voltage in a scanning signal Vg(j) as shown in FIG. 23A, from a gate ON voltage Vgh to a gate OFF voltage Vgl, will cause a level shift ΔVd as shown in FIG. 23C, in the electric potential of the pixel electrode (pixel electric potential) Vd due to the parasitic capacity Cgd. (This ΔVd is also called “field-through voltage.”) The level shift ΔVd is given by the following mathematical expression:ΔVd=(Vgh−Vgl)·Cgd/(Clc+Cs+Cgd)  (1)
The parasitic capacity Cgd, i.e. the gate-drain capacity Cgd, in the mathematical expression given above differs from one segmented region to another corresponding to segmentation at the time of separate exposure as already described, and therefore, the level shift ΔVd also differs among these segmented regions. As a result, the same data signal will cause different transmissivity (display luminance) of the liquid crystal layer in different segmented regions, in a liquid crystal display device which uses such an active matrix substrate. This phenomenon, which is sometimes called “block segmentation” (or “tiling”), decreases display quality. There is a further implication in the liquid crystal display device in which polarity of the voltage applied to the liquid crystal layer is inversed for each predetermined period. Specifically, in this inversion arrangement, electric potential of the opposed electrode is made lower than the center potential of the data signal line by an amount of the above-described level shift, so that the voltage applied to the liquid crystal will be substantially symmetric in positive and negative polarities. Therefore, differences in the level shift ΔVd among the segmented regions will unavoidably result in a situation that the asymmetry correction is imperfect in some of the regions, leading to a problem of flickering (of the display) which decreases display quality.
There have been a number of proposals in an attempt to solve such a problem. For example, Patent Document 1 listed below discloses an active matrix substrate as a background of that patented invention, where a pixel formation portion (hereinafter may also called “pixel” for simplicity) is constituted by two subpixels. Each of the two subpixels is provided with a TFT switching element, and the two TFTs are built in such a way that their capacities, which are equivalent to the parasitic capacity Cgd and are held in the two respective subpixels, will have values of a reverse relationship in terms of increase/decrease with respect to the pattern misalignment in a given direction (See FIG. 8 in Patent Document 1, for example).
In another proposal which was made also in an attempt to solve the above-described problems, an active matrix type display device has for each pixel a new capacity (called “compensating capacity” for example) which makes up for the difference caused by pattern misalignment of a parasitic capacity that is equivalent to the parasitic capacity Cgd. A compensating capacity is connected in parallel to the parasitic capacity, so that there is always a constant sum of the parasitic capacity and the compensating capacity even if there is a pattern misalignment. (See Patent Documents 1, 2 and 3 for example, listed below.)
Further, Patent Document 4 listed below proposes a delta-arrangement liquid crystal display panel including an active matrix substrate in which self-alignment formation technique is utilized in making TFT channel regions in order to reduce unnecessary parasitic capacities thereby reducing inconsistency among the parasitic capacities due to separate exposure, etc.
Still further, Patent Document 5 listed below proposes a TFT array substrate as an active matrix substrate, where each pixel has a TFT which has a narrow part that straddles over a semiconductor layer and a gate electrode end of drain wiring formed on the semiconductor layer. The narrow part is narrower than a TFT channel width, i.e., a drain electrode width.
Patent Document 1 U.S. Pat. No. 5,285,302
Patent Document 2 JP-A 6-27487 Gazette
Patent Document 3 JP-A 6-110081 Gazette
Patent Document 4 JP-A 8-87026 Gazette
Patent Document 5 JP-A 2002-14371 Gazette
However, active matrix substrates such as those disclosed in Patent Documents 1 through 3 have a problem. Specifically, these substrates use an arrangement that each pixel is constituted by a plurality of subpixels each including a TFT, whereby an increase/decrease in the gate-drain capacity Cgd, i.e. in the parasitic capacity due to pattern misalignment, is reduced within each pixel; or that each pixel has a new capacity (compensating capacity for example) which compensates for an increase/decrease in the gate-drain capacity Cgd, i.e. in the parasitic capacity. These arrangements which require formation of a TFT in each of the subpixels or formation of a new capacity in each pixel result in increased area of non-light-transmittance (e.g. the area occupied by the TFTs) in each of the pixels. This means that a liquid crystal display panel which uses the active matrix substrate has a decreased aperture ratio.
Also, the above-described conventional active matrix substrates have an increased parasitic capacity Cgd per pixel as a result of the formation of a TFT and the formation of a new capacity in each pixel. This also increases the level shift ΔVd (absolute value) (of the pixel electric potential) given by the mathematical expression (1), making it difficult to correct the level shift ΔVd by an electric potential Vcom applied to the opposed electrode Ec, resulting in such problems as deterioration of the liquid crystal caused by a direct current component applied to the liquid crystal layer, decreased display quality caused by flickering, etc. Another problem caused by increased parasitic capacity Cgd is increased delay in signal propagation, such as in scanning signals in the scanning signal lines and data signals in the data signal lines. These delays also decrease quality of display. Further, increased parasitic capacity per pixel leads to increased power consumption in the drive circuit of the active matrix substrate. Further, formation of a TFT for each subpixel and formation of a new capacity for each pixel require complicated mask patterns in the manufacture of the active matrix substrate, and can decrease production yield of the active matrix substrate.
According to the active matrix substrate included in the liquid crystal display panel disclosed in Patent Document 4, color arrangement is limited to the delta arrangement. Further, since the TFT's channel region is formed by means of self-alignment, a special manufacturing process which is different from common process is required.
Then, according to the TFT substrate serving as an active matrix substrate disclosed in Patent Document 5, an arrangement which provides improved patterning for TFT formation decreases parasitic capacity, and thereby decreases parasitic capacity inconsistency caused by pattern misalignment. However, the decrease in parasitic capacity inconsistency achievable by such an improvement alone is not sufficiently more significant than the levels achieved by the other conventional techniques described above, and so it is not possible to provide a satisfactory solution to the problems of block segmentation and annoying levels of flickering.